Expertise in Front-end RTL design and SoC integration of multi-million gates IPs and SoCs for a variety of industry verticals like mobile, processors, networking and multimedia.

Fabrication-ready designs that meet area, speed and power requirements. From RTL design, simulation to generation of the GDSII files.

CoreIC verification team has expertise on taking ownership of verification of a design from scratch – whether that is an IP/SOC/subsystem and taking it to verification closure.

• Understanding the design architecture specification and creating the verification Plan, Environment, Test Bench Development.
• SV-UVM Based Random Verification at IP/SS/SOC.
• C-Based verification at SOC level.
• Low Power Verification using CPF & UPF.
• Gate Level simulation
• Assertion based Formal Verification using SVA & PSL
• VIP Development and Integration.
• Analog/mixed-signal block simulations, Modelling of analog and mixed signal blocks using Verilog-AMS.
• Verification closure through corner case verification, coverage closure and regression closure